Hardware-software co-design of an iris recognition algorithm

摘要

This paper describes the implementation of an iris recognition algorithm based\udon hardware-software co-design. The system architecture consists of a general-purpose 32-\udbit microprocessor and several slave coprocessors that accelerate the most intensive\udcalculations. The whole iris recognition algorithm has been implemented on a low-cost\udSpartan 3 FPGA, achieving significant reduction in execution time when compared to a\udconventional software-based application. Experimental results show that with a clock\udspeed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480\udpixels, which is just 20% of the total time needed by a software solution running on the\udsame microprocessor embedded in the architecture.